Hackathon solutions

Hands-on: Read PCI register

Solution:

+#include "mypcidump.h"

 void late_mainboard_romstage_entry(void)
 {
-
+       mypcidump();
 }

src/mainboard/ocp/wedge100s/romstage.c

 #include <device/device.h>
+#include "mypcidump.h"
+
+static void mainboard_init(struct device *dev)
+{
+       mypcidump();
+}
+

 static void mainboard_enable(struct device *dev)
 {
-
+       dev->ops->init = mainboard_init;
 }

src/mainboard/ocp/wedge100s/mainboard.c

src/mainboard/ocp/wedge100s/Makefile.inc

+ramstage-y += mypcidump.c
+
+romstage-y += mypcidump.c

Hands-on: Read PCI register

Solution:

+#include <device/device.h>
+#include <device/pci_ops.h>
+#include <device/pci_def.h>
+#include <device/pci.h>
+#include <console/console.h>
+#include "mypcidump.h"
+
+void mypcidump(void)
+{
+#ifdef __SIMPLE_DEVICE__
+       pci_devfn_t dev = PCI_DEVFN(20, 0);
+#else
+       struct device *dev = dev_find_slot(0, PCI_DEVFN(20, 0));
+#endif
+
+       printk(BIOS_DEBUG, "PCI_DEVICE_ID 0x%x\n",
+              pci_read_config16(dev, PCI_DEVICE_ID));
+       printk(BIOS_DEBUG, "PCI_BASE_ADDRESS_0 0x%x\n",
+              pci_read_config32(dev, PCI_BASE_ADDRESS_0));
+}

src/mainboard/ocp/wedge100s/mypcidump.c

Hands-on: Read raw values from FMAP region

Solution:

+#include <fmap.h>
+#include <console/console.h>
 /*
  * mainboard_enable is executed as first thing after enumerate_buses().
  * This is the earliest point to add customization.
  */
 static void mainboard_enable(struct device *dev)
 {
+       struct region_device rdev;
+       u8 *data;
+       size_t len;
 
+       if (fmap_locate_area_as_rdev("COREBOOT", &rdev) == 0) {
+               data = rdev_mmap_full(&rdev);
+               len = region_device_sz(&rdev);
+               printk(BIOS_DEBUG, "FMAP COREBOOT: ");
+               for (int i = 0; i < 8 && i < len; i++)
+                       printk(BIOS_DEBUG, "%c", data[i]);
+               printk(BIOS_DEBUG, "\n");
+               rdev_munmap(&rdev, data);
+       } else
+               printk(BIOS_ERR, "Failed to find FMAP region\n");
 }

src/mainboard/ocp/wedge100s/mainboard.c

FMAP COREBOOT: LARCHIVE

 

Hands-on: Add FMAP MRC cache

src/mainboard/ocp/wedge100s/board.fmd

Solution:

                FMAP@0x0 0x1000
-               RW_MISC@0x1000 0xe000 {
+               RW_MISC@0x1000 0x2e000 {
                        RW_ELOG@0x0 0x4000
                        RW_VPD@0x4000 0x2000
                        RW_MISC_UNUSED@0x6000 0x5000
                        RW_NVRAM@0xc000 0x2000
-#                      UNIFIED_MRC_CACHE@0x10000 0x20000 {
-#                              RECOVERY_MRC_CACHE@0x0 0x10000
-#                              RW_MRC_CACHE@0x10000 0x10000
-#                      }
+                       UNIFIED_MRC_CACHE@0xe000 0x20000 {
+                               RECOVERY_MRC_CACHE@0x0 0x10000
+                               RW_MRC_CACHE@0x10000 0x10000
+                       }
                }
-               UNUSED@0xf000 0x1000 {
+               UNUSED@0x2f000 0x1000 {
                        # This only exists to satisfy tools that
                        # specifically look for RO_VPD.
                        RO_VPD@0x0 0x1000
                }
-               COREBOOT(CBFS)@0x10000 0x7f0000
+               COREBOOT(CBFS)@0x30000 0x7d0000
        }

src/mainboard/ocp/wedge100s/Kconfig

+       select MRC_CACHE_FMAP

Hands-on: Add FMAP MRC cache

FMAP: area RW_MRC_CACHE found @ 81f000 (65536 bytes)
find_current_mrc_cache_local: No valid fast boot cache found.
FSP MRC cache not present.

Solution:

first boot:

second boot:

FMAP: area RW_MRC_CACHE found @ 81f000 (65536 bytes)
find_current_mrc_cache_local: picked entry 0 from cache block
FSP MRC cache present at ff81f000.
romstage_main_continue status: 0  hob_list_ptr: 7f100000

Hands-on: Fix SPI console

Solution:

+#include <device/pci_def.h>
+#include <arch/early_variables.h>


-static int ichspi_lock = 0;
+static int ichspi_lock CAR_GLOBAL = 0;
 
-static ich_spi_controller cntlr;
+static ich_spi_controller cntlr CAR_GLOBAL;


-#ifdef __SMM__
+#if defined(__SIMPLE_DEVICE__)

/src/soc/intel/fsp_broadwell_de/spi.c

src/soc/intel/fsp_broadwell_de/Makefile.inc

+romstage-y += spi.c

-               COREBOOT(CBFS)@0x10000 0x7f0000
+               CONSOLE@0x10000 0x10000
+               COREBOOT(CBFS)@0x20000 0x7e0000
        }

src/mainboard/ocp/wedge100s/board.fmd

src/soc/intel/fsp_broadwell_de/Kconfig

+       select TSC_CONSTANT_RATE

https://review.coreboot.org/#/c/coreboot/+/25046/

Solution:

Hands-on: Missing VPD support

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